1. Field of the Invention
The present invention relates to data processing systems, and more particularly to counting predetermined instructions fetched and/or executed by a processor.
2. Description of the Prior Art and Related Information
In designing computer hardware and software, designers find it useful to measure performance characteristics of the computer system so that deficiencies may be diagnosed and corrected, and performance otherwise maximized. For example, the designer may wish to count the number of trap instructions indicating that a floating point result has gone out of range and determine where in the program code this error is occurring. If a particular section of code results in the execution of an excessive number of trap instructions, that section may need to be modified. Counting of other instructions is also useful in optimizing system performance.
One prior art performance measuring technique uses software to single step through the application program being tested. Each instruction is fetched and decoded. Control is then transferred back to a monitoring program, which compares the decoded opcode to a predetermined opcode taken from a predefined set of opcodes. If a match is found, a counter associated with the matched opcode from the set is incremented. After the monitoring program has completed this procedure, control is turned back to the application program for fetching and decoding of the next instruction. Shuttling back and forth between monitoring and execution of application programs degrades execution speed.
One hardware technique that is used to count the type of instructions being executed relies upon a special bit included in the instruction set. For example, in some processors a single bit flag in the opcode is set to indicate that the opcode represents a floating point instruction. At the decode stage, logic in the decode unit increments a counter every time it detects this flag. This method can be expanded to include any type of instruction, but is limited in that it requires modification of the instruction set to include the flag bits.
Another hardware technique counts processor events. One processor chip manufactured by Intel Corporation, the assignee of the present invention, includes a set of control registers that can be programmed to specify the events to be counted, such as cache misses, floating point operations, or the execution of branch instructions. Each time a predetermined event occurs, a counting register is incremented. For example, if floating point operations are to be counted, during execution of instructions the processor determines whether the floating point arithmetic logic unit and associated control structures are being utilized. To count branching operations, the processor determines whether the instruction pointer is being incremented in a non-sequential manner.
Based on the foregoing, the prior art clearly exhibits a number of drawbacks. Using performance monitoring software to single step through the application program drastically slows system performance. As for the first hardware technique, that method requires flag bits to be added to the opcode for each parameter to be measured, thereby limiting the instruction codes that are to be counted by the available opcode length. Finally, the technique utilized by the prior art Intel chip requires that logic circuitry monitor different areas of the chip to determine what events are occurring during execution.
It would be desirable to have a more flexible and comprehensive means for counting instructions being fetched by a processor. The prior hardware methods are limited to counting the type of instructions being executed, e.g., floating point instructions. However, designers would benefit by knowing what particular instructions within a type are present. For example, a count of executed floating point add, subtract and multiply instructions would permit the megaflop rate of the code to be calculated. In addition, by counting individual instructions, one can also determine whether certain instructions are never executed and thus may be eliminated from the instruction set.
Using information concerning individual instructions, the designer could also easily perform test coverage analysis by running an application program that executes every instruction. By comparing the count for each instruction with the number of times that instruction occurs in the code, the designer could determine whether the instructions are executing properly.